Parallel Programming and Optimization for Intel® Xeon Phi™ Coprocessors
This professional training is designed for programmers who are looking to develop skills in application design and optimization for Intel® Xeon Phi™ coprocessors.
Participants will be provided with an introduction to available programming models, the tools and the knowledge needed to accelerate highly-parallel algorithms by taking advantage of the Intel® Many Integrated Core (Intel® MIC) Architecture. A combination of lectures, case studies and hands-on exercises will provide participants with an understanding of:
- Intel® Xeon Phi™ Coprocessor architecture
- Available execution models including offloading and native execution
- Memory models including using pragmas and virtual-shared memory
- Debugging and profiling tools
- Optimization techniques for both memory bandwidth and compute bound algorithms
This professional course has been built from Acceleware’s 9 years of parallel development experience and recognized teaching methods to fast-track participant’s programming skills for Intel® Xeon Phi™ coprocessors. The course content has been established in collaboration with Intel® and includes commercial optimization techniques developed by Acceleware.
Training courses coming soon! Please contact us for more information.
Acceleware training for Xeon Phi™
in partnership with Intel
“The instructor is gifted and has broad experience. He is excellent at answering questions in context.”
Bill Ward
LANL
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